1. Field of the Invention
The present invention relates to a semiconductor test apparatus for implementing testing of a semiconductor through a plurality of electrode pins.
2. Description of the Related Art
FIG. 12 is a block diagram showing a conventional semiconductor test apparatus. In the figure, reference numeral 10 is the measured device (hereinbelow, referred to as a DUT), and the semiconductor test apparatus measures a waveform obtained by applying a test waveform to each of the electrode pins 12-1, 12-1, . . . 12-n, of this DUT 10, or measures a waveform generated by the DUT 10. Then, by comparing this measured result to an expected value, measurement of the DUT or a determination of product acceptance or rejection is carried out. The test blocks 60-1, 60-2, . . . , 60-n apply a test signal to each pin of the DUT 10 or input a test signal generated by the DUT 10. The control circuit 54 controls the data and the operational timing of this plurality of test blocks 60-1 to 60-n based on the control of the host CPU.
Next, the operation of this conventional semiconductor test apparatus will be explained for the case in which the test waveform sent to the electrode pins 12-1 to 12-n is a digital signal. First, a timing generating circuit 53 generates the timing of the data applied to the DUT 10 or received from the DUT 10. The reading or writing of the content of the data memory 55 is carried out in synchronism with the clock of the PLL circuit 59 depending on the content of the control memory 56. Here, the digital pattern applied to the DUT 10 and the amount of delay for indicating the phase of this digital signal are written into the data memory 55. The content of the control for multiple execution of an indicated arbitrary portion of the content of the data memory 55 is written into the control memory 56.
The data read out from the data memory 55 is input into the delay circuit 57 via the control circuit 54. The delay circuit 57 generates a digital signal having an indicated delay value in synchronism with the output clock of the PPL circuit 59 based on the pattern data and the delay amount setting data output from the control circuit 54, and this is input into the pin 12-1 of the DUT 10 via the DUT driver 58.
The test blocks 60-2 to 60-n are identical circuits, and the signals respectively generated thereby are input into the electrode pins 12-2 to 12-n of the DUT 10. Moreover, although not illustrated in the figure, the signals generated by the DUT 10 are respectively written into the data memory 55-1 to 55-n in a sequence opposite to that of the signal flow described above. Then the differences between these signals and the expected values are written into the respective data memory 55-1 to 55-n. In addition, although not illustrated in the figure, an identical operation is carried out for analog signals or a power source.
However, in such a conventional semiconductor test apparatus, because the exchange of the signals between each of the test blocks 60-1 to 60-n must be carried out via the control circuit 54 and real time processing in synchronism with a clock is necessary, there are the problems that the structure of this control circuit 54 becomes complicated and large in scale, and in addition, providing both data memory 55 and control memory 56, which is the timing memory, is necessary.
In addition, the data memory 55 and the control memory 56 must carry out reading and writing in real time, and thus the use, for example, of memory that requires a refresh operation such as dynamic RAM is difficult, and furthermore, treating data that exceeds the capacity of the data memory 55 and the control memory 56 for a particular pin is difficult. Thus, there is the problem that in order to resolve these difficulties in conventional technology, the capacity of the memory must be increased, or the output signals of the other test blocks must be switched and output by the control circuit 54.
Furthermore, in order to transfer data from the host CPU to the memory of each of the blocks 60-1 to 60-n, signal switching control for transferring data to the object blocks 60-1 to 60-n via the control circuit 54 is necessary. In addition, the control circuit and devices must be changed depending on the type (analog or digital) of the signals of the DUT 10. In addition, there is the inconvenience that depending on the number of signals of the DUT 10, the number of circuits must be increased arbitrarily.
In order to resolve the above described problems, it is an object of the present invention to provide a semiconductor test apparatus whose structure does not use a complicated or large scale control circuit or control memory, can reduce the circuits for real time processing, and at the same time allows use of refresh memory, can allot a large amount of data to a particular electrode pin of the measured device without adding memory, and can realize this in a comparatively simple structure.
In order to attain the above-described object, a semiconductor test apparatus according to the present invention provides a plurality of test blocks that comprise a data processing apparatus (in the present embodiments, the digital signal processor (DSP) and the microprocessor (CPU)) provided for each of the electrode pins of the measured device, memory that stores test pattern data, the delay amount setting data, and the control pattern data, and carries out reading and writing of this data under the control of the data processing apparatus, a first-in-first-out element that executes the queue processing of the serial signals that are the serially processed data read out from the memory, a delay circuit that delays the output signal of the first-in-first-out elements at a timing in synchronism with a reference clock, and a measured device driver that inputs the output signal of the delay circuit into the electrode pins of the measured device, and in which the data processing apparatus of each of the adjacent test blocks are connected together into a loop via an input-output circuit provided on each of these test blocks.
In addition, the semiconductor test apparatus according to the present invention provides a plurality of test blocks comprising a data processing apparatus provided for each of the electrode pins of the measured device, memory that stores the expected value data and the phases of the measured device, and carries out the reading and writing of the data under the control of the data processing apparatus, first-in-first-out element that executes queue processing of the serial signals that are serially processed data read out from the memory, and a measured device receiver that compares the expected value data obtained from the first-in-first-out element to output signals received from the electrode pin of the measured device, outputs a signal indicating whether or not they agree, and stores the result in the memory via the first-in-first-out element, and in which the data processing apparatus of each of these adjacent test blocks are connected together into a loop via the input/output circuit provided on each of the test blocks.
In addition, the semiconductor test apparatus according to the present invention provides a plurality of test blocks comprising a data processing apparatus provided for each of the electrode pins of the measured device, memory that stores the test pattern data, the delay amount setting data, and the control pattern data, and carries out reading and writing of the waveform data of the data under the control of the data processing apparatus, a first-in-first-out element that executes queue processing of serial signals that are serially processed data read from the memory, and a digital/analog conversion circuit that converts the output signal of the first-in-first-out element to an analog signal and inputs the result into the electrode pins of the measured device at a timing in synchronism with a reference clock, and in which the data processing apparatus of each of the adjacent test blocks are connected together into a loop via the input/output circuit provided on each of the test blocks.
In addition, the semiconductor test apparatus according to the present invention provides a plurality of test blocks comprising a data processing apparatus provided for each of the electrode pins of the measured device, an analog/digital conversion circuit that converts an analog output signal received from an electrode pin of the measured device to a digital signal at a timing in synchronism with a reference clock, first-in-first-out element that executes queue processing of the output signal of the analog/digital conversion circuit, and memory that stores the output signal of the first-in-first-out element based on the control of the data processing apparatus, and in which the data processing apparatus of each of the adjacent test blocks are connected together into a loop via the input/output circuit provided on each of the test blocks.
In addition, in the semiconductor test apparatus according to the present invention, the data processing apparatus supplies in parallel to each of the electrode pins of the measured device via each of the individual measured device drivers a plurality of types of data that is stored in the memory.
In addition, in the semiconductor test apparatus according to the present invention, the plurality of test blocks are partitioned into a part having common circuits for all of the blocks and part having circuits that differ depending on the measurement conditions.
In addition, in the semiconductor test apparatus according to the present invention, the plurality of test blocks are connected to each other via connectors having terminals identical to the printed circuit board on which the data processing apparatuses are mounted.
In addition, in the semiconductor test apparatus according to the present invention, the data processing apparatus is a digital signal processor (DSP) or a microprocessor (CPU).
In addition, in the semiconductor test apparatus according to the present invention, the read-out speed of the memory controlled by the data processing apparatus is set so as to be slightly faster than the average output interval of the first-in-first-out elements.
In addition, in the semiconductor test apparatus according to the present invention, identical trigger signals are input into all of the data processing apparatuses.